When a power supply is switched on a logic circuit being powered can initially be set to some random, non-functional logic order if the logic circuit has no power-on-reset circuit coupled thereto which controls initial conditions of the logic circuit. Therefore, a power-on-reset circuit is normally provided to set the logic to a preselected functional order.
FIG. 1 shows a prior art power-on-reset circuit 10 (with a dashed line rectangle) connected by a POR output terminal to a reset terminal 18 of an integrated circuit (IC) 19. Circuit 10 comprises a resistor 12, a capacitor 14 and an inverter 13. Inverter 13 is typically a Schmitt trigger. A first terminal of resistor 13 and first power supply terminals of the inverter 13 and the IC 19 are coupled to a first voltage source (power supply) Vdd and to a terminal 16. A second terminal of the resistor 12 is coupled to a first terminal of the capacitor 14, to an input of inverter 13, and to a terminal 15. A second terminal of the capacitor 14 and second power supply terminals of the inverter 13 and the IC 19 are connected to a second voltage source (power supply) Vss and to a terminal 17. In an illustrative embodiment Vss=0 volts (ground potential) and Vdd is switched from an off state of 0 volts to an on state of +5 volts.
FIG. 2 shows the voltage of Vdd (terminal 16) versus time with Vdd rising from 0 volts at time=t1 to +5 volts at time=t3. FIG. 3 shows the voltage of terminal 18 versus time as Vdd switches as is shown in FIG. 2. Prior to time=t1, the input and output of inverter 13 are both "0's" since it is assumed that there has been no power on for a period of time and all terminals have settled to 0 volts. For rise times of Vdd that are relatively short compared to the time constant of the resistance (R) of resistor 12 and the capacitance (C) of capacitor 14, inverter 13 is turned on as Vdd becomes positive enough to bias on inverter 13. As inverter 13 is being biased on and terminal 15 is still at or close to 0 volts, a "0" or low, the output of inverter 13 starts (at time=t2) to increase from 0 volts and reaches +5 volts, a " 1" or high, by time=t4. As terminal 15 reaches +5 volts, a "1", inverter 13 changes output states and terminal 18 is set to a "0" (by time=t5). Thus circuit 10 functions to set reset terminal 18 of IC 19 to a "1'" which is then followed by a "0".
If the rise time of Vdd is relatively long compared to the R-C time constant of the resistor 12 and the capacitor 14, then inverter 13 begins to turn on as the voltage of terminal 15 rises and thus the output of inverter 13 can in some cases stay at a "0" and does not rise to the needed "1". This prevents IC 19 from being reset and thus can cause a failure in the proper operation of IC 19.
It is desirable to have a power-on-reset circuit which provides the needed sequence of logic levels independent of the rise time of a voltage source (power supply) used therewith.